1. Field of the Invention
The present invention relates generally to semiconductor integrated circuits, and more specifically to an output driver circuit suitable for use with high speed devices.
2. Description of the Prior Art
As integrated circuits become faster, various factors become important to their operation which are not important at slower speeds. For example, in CMOS integrated circuits, an output circuit connected to the output pad of a chip typically includes one P-channel device and one N-channel device stacked in series. When such output changes state very quickly, current changes occur which have a very steep slope. The rate of change of current, referred to as di/dt, combines with inductance of the output pin and the power supply connected to the output driver to cause a voltage jump which reflects into the power supply. This voltage jump is often referred to as ground bounce.
Since the voltage jump is defined by L(di/dt), it is known that limiting the slope of the output current can help minimize the problem. In order to limit the rate of change of the output current, it is known to limit the switching speed of the output transistors. This is often done by causing the last stage of the output circuitry, which drives the gates of the output transistors, to switch more slowly than usual. This causes the output transistors to turn on and off more slowly, lowering di/dt, and limiting the voltage jump. Even though the changing of state of the output circuit is slowed down, overall speed of the device may actually increase because a long settling time is not needed to recover from the ground bounce phenomenon.
This switching speed limitation of the logic stages driving the output transistors is sometimes referred to as slew rate control.
One technique for controlling the slew rate of the output stage is to place resistors in the supply path to the final stage of logic gates. These resistors cause the logic gates to change state more slowly, which slows the rate of change of voltage to the gate of the output transistors. Thus, as described above, the output transistors change state more slowly, limiting di/dt.
One drawback to this approach, however, is that the use of the limiting resistors tends to slow down the output circuitry more than desired. The value of these resistors must be chosen to decrease the steepest part of the slope of the output from the last logic stage, which requires fairly large resistors. However, this also slows down operation of the final logic stage for portions of the output curve where di/dt limiting is not really required.
It would be desirable to provide an output driver circuit which limits di/dt to sufficiently low values, while providing a circuit which otherwise has maximum speed. It would be further desirable for such a circuit to be formed without adding undue complexity to the output driver portion of the device.